1. Field of the Invention
The invention generally relates to electrical circuit design, and more particularly to a system and method for using direct fit and interpolated models in analyzing and designing electrical circuits.
2. Description of the Related Art
In order to create better circuits, circuit designers must depend on improved transistor models. However, circuit designers are seldom privy to information on how the models were generated such as device sizes that were characterized and their bias conditions. Seldom does the circuit designer have information about how the model was constructed, which device sizes (length, width, finger length) were directly characterized, and which device sizes are interpolated from characterized data. In addition, conventional device models typically employed in simulation are constructed to interpolate device performance parameters over a large number of physical, electrical, and environmental variables such that all devices in the netlist use the same generalized model. While this conventional approach eases simulation problems it does not provide optimal accuracy for device sizes which are actually characterized or provide the design information on what device topologies contributed to the model, which all lead to inaccuracy in simulation.
Therefore, due to the drawbacks and limitations of the conventional systems and methods there remains a need for a novel system and method for transistor level simulation to aid electrical circuit engineers in the design and analysis of circuits.